Seyed Mohammad Seyedzadeh

  Abstract

  Security information in the satellite images is rapidly growing and has been the focus of many researches. Illegal access to satellite networks for the purpose of accessing satellite data has proved the vulnerability of most of these data to Hacking threats. To overcome these threats, the security of satellite data can be achieved by encryption. Currently, most of the Earth Observation (EO) Satellites are equipped with the onboard encryption system for protection of the data that are transmitted to the earth Stations. Regarding to the fact that satellites operate in the Harsh Radiation Environment, each electronic onboard system and typically encryption processors are prone to Single Event Upsets.

  To increase the Fault Tolerance of the AES algorithm in the encryption of satellite image, this thesis proposes architecture based on the Hamming code error detection and correction method. This architecture can detect and correct single bit fault through the encryption process. The architecture uses a module for the detection and correction of faults in each transformation in each round of the AES algorithm. This module detects and corrects the fault that occurs during the encryption.

  The fault propagation in the proposed architecture is simulated by a java program and then validated in 5 operation modes of the AES algorithm. Synthesizing of this architecture was done by the ISE software. The value of Efficiency, Overhead, Throughput, Maximum Frequency, and Power were 1.1 Mbps/slice, 16%, 24.2 Gbps, 188.718 MHz, and 1232 mW respectively. These results show that the proposed architecture has more satisfactory performance than the other architectures mentioned in the thesis.

  Date of Defense: March 5, 2011 Time:13

  Place: Class 305 Faculty of electrical engineering