Yasser Baleghi Damavandi

AWT IMAGE
Electrical Department

  PhD Thesis Defense Session

  AWT IMAGE

  Design and Simulation of Evolvable Hardware and Its Communication Protocol

  Abstract

  A Permanent physical fault in the communication line between two agents can usually lead to failure. In this thesis a kind of self organized communication is proposed to defeat the problem.

  In this case, the communication protocol that emerges between the agents can adapt itself to environmental changes like physical faults. To evolve such an emergent communication, agents should have knowledge representation language, be purposeful and rational. Evolvable hardware agents own all of the mentioned properties. Evolvable hardware is a concept that aims the use of evolutionary algorithms in the hardware design.

  In this thesis, the mentioned agents are simulated and implemented to emerge a self organized protocol which is expected to be fault tolerant. The simulations show good results in gate level evolution of a fault tolerant serial adder. However, the idea of hierarchical level evolution is proposed in this dissertation and tested in another experiment to defeat the shortcomings of gate level and functional level evolution in the application of transferring video streams. Using hierarchical level evolution in genetic algorithm, stalling effect is removed to some extent and a self organized, fault tolerant communication is emerged to transmit the images between evolvable hardware agents.

  In this system, redundancies are added autonomously to hardware and consequently to the communication protocol. The agents emerged variant mappings to tolerate different faults at the expense of more evolution time.

  Student: Yasser Baleghi Damavandi

  Supervisor:

  Dr. Karim Mohammadi

  Advisor:

  Dr. Caro Lucas

  Reviewers: Dr.Sahebzamani, Dr.Taheri, Dr.Shokouhi,Dr. Sadr, Dr. ShahHosseini

  Date : 2010/03/07 Time: 16:30

  Place: Seminar Conference Room

 


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